The present invention relates to a wireless receiver, in particular as part of a wireless transceiver.
There is an increasing need for energy efficient homes, offices and industrial plants. Energy efficiencies can be achieved through the deployment of wireless sensor network (WSN) systems, which allow for building automation, industrial monitoring and many other applications. To address this market, the 2.4 GHz IEEE 802.15.4 worldwide wireless standard has been defined, which specifies a short-range low-power wireless protocol. To conform to the standard, electronic devices will need to be developed which integrate radio-frequency (RF) electronic components, micro-controllers, on-chip sensors and sensor interfaces. For commercial reasons, this integration will need to be done on a single integrated circuit, i.e. on a single chip.
A wireless or radio transceiver conforming to IEEE 802.15.4 should utilize its transmitted power resource to maintain a satisfactory signal power at an associated transceiver. The efficiency of the transceiver is known as power efficiency. The magnitude of signal power required at the receiver is determined by the sensitivity of the receiver. Receiver sensitivity is defined as the minimum signal power at the antenna that results in an error performance defined by the standard. Since receiver sensitivity is proportional to nf; the noise factor of the receiver, and SNRmin, the minimum baseband signal-to-noise ratio at the demodulator, keeping either value to a minimum will result in greater power efficiency. The minimum signal power Pmin is specified by:Pmin=kT*BW*nf*SNRmin                 where:        kT=−174 dBm @ 25° C.;        BW=communication bandwidth (equivalent to chip rate for 802.15.4)=2 MHz;        nf=receiver front-end overall noise figure (≧1); and        SNRmin=minimum signal power-to-noise ratio at detector/demodulator input.        
Minimizing the value of receiver nf requires the noise factor of amplifiers, mixers and filter circuits in the receive path to be kept to a minimum bearing in mind that gain also needs to be kept sufficiently high for reliable operation. However, the noise and gain performance of these receiver circuits are proportional to circuit power consumption. Moreover, minimizing the SNRmin of a receiver necessitates a demodulator design having a multi-bit representation of the baseband signal. The number of bits in an analog-to-digital converter (ADC) required to produce this multi-bit representation is similarly proportional to circuit power consumption. Designing a low-power transceiver therefore involves a trade-off between transceiver power efficiency and receiver noise performance, and therefore circuit power consumption.
In the prior art, both direct conversion and low-intermediate frequency (IF) receiver architectures have been used in integrated low-power transceivers [1, 2]. The direct conversion technique requires low design complexity. However, it is particularly susceptible to noise and non-linearities in the mixer circuit, resulting in a high receiver nf. This architecture has been shown to achieve the required minimum IEEE 802.15.4 sensitivity specification, but with little margin [3]. Hence this architecture is limited in its ability to trade power efficiency against noise performance.
Two baseband decoding or demodulation schemes are used in low-IF receiver topologies, these being known as coherent and non-coherent. Coherent schemes require the signal to have a high degree of coherency, i.e. to be relatively free of timing errors such as phase jitter or frequency variation. Non-coherent schemes are designed to be resilient against timing errors. Coherent schemes can achieve values of SNRmin that approach the theoretical limit, but this is achieved at the expense of higher circuit power consumption due to the need for a relatively complex receiver topology and the requirement for a relatively high ADC resolution of around 8 bits. Non-coherent schemes however trade a high value of SNRmin in return for low circuit power consumption due to a simpler receiver topology and lower ADC resolution requirements.
FIG. 11 is a schematic drawing of a prior art coherent scheme as described by Koteng [4]. The coherent demodulator comprises a channel filter 1102 connected to the output of the radio frequency (RF) front-end of the transceiver (not shown). The channel filter 1102 is fed by an in-phase component of the digital baseband signal (IBB) and an out-of-phase component of the digital baseband signal (QBB). The channel filter is generally used to attenuate all the channels and noise outside the wanted channel. The channel filter 1102 is connected to a frequency and phase compensator 1104. The frequency and phase compensator 1104 is further connected to a frequency and phase estimator 1106. The frequency and phase estimator 1106 is used to estimate the frequency and phase of the incoming baseband signal. The frequency and phase compensator 1104 is used to correct the continuous rotation of the signal constellation of the received signal, which results from a transmitter and receiver local oscillator offset at the receiver. The frequency and phase estimator 1106 also detects the preamble in the received signal, which is used for frequency and phase compensation. The frequency and phase compensator 1104 is connected to a correlator 1108. The correlator 1108 compares the values of the IBB and QBB signals with the 32 bit-chip values of the 16 symbols specified by the IEEE 802.15.4 standard. These 32 bit-chip values are stored in a look-up table accessible by the correlator 1108. The correlator 1108 is connected to a maximum decision unit 1110. The maximum decision unit 1110 takes the result from the correlator 1108, i.e. the correlation between the baseband signal and the chip values of the 16 symbols, and makes a decision regarding which symbol has been transmitted. This may be achieved by the maximum decision unit 1110 by finding the maximum correlation value. The symbol having the maximum correlation value is then fed to a frame synchronization unit, or frame sync unit 1112. The frame sync unit 1112 may use the correlation for the zero-symbol to ensure the correct timing such that the subsequent symbols are in sync with the zero-symbol.
The coherent demodulator described above has a simpler correlation algorithm compared to a non-coherent demodulator in that it uses a single correlation rather than a double correlation. A single correlation can be carried out using the following relationship for the correlation function C(s):
      C    ⁡          (      s      )        =            ∑              n        =        d            31        ⁢                  y        n            *              s                  s          ,          n                    where ‘y’ is the received baseband signal and ‘s’ is pseudo-random noise (PN) direct sequence spread-spectrum chip code of the symbols specified by the IEEE 802.15.4 standard.
However, the phase and frequency compensator 1104 and the frequency and phase estimator 1106 required before the correlator 1108 result in a high required signal resolution and high complexity of hardware. Furthermore, the phase and frequency estimation needs to be completed during the preamble (i.e. during training) and insufficient correction accuracy will results in loss of functionality.
FIG. 12 is a schematic drawing of a prior art non-coherent scheme as described by Han and Choi [5]. The non-coherent demodulator comprises a delay and differential filter 1202 that is fed by the two baseband signals IBB and QBB. The differential filter 1202 is connected to a phase and frequency estimator 1206 and a phase and frequency compensator 1204. The phase and frequency compensator 1204 compensates for the frequency offset based on the estimated frequency offset from the phase and frequency estimator 1206. The phase and frequency estimator 1206 also performs preamble detection for detecting the transmitted preamble. The preamble detection is used to compensate the phase and frequency. Connected to the phase and frequency compensator 1204 is a double-correlator 1208. The double-correlator 1208 compares the values of the IBB and QBB signals with the 32 bit-chip values of the 16 symbols from the IEEE 802.15.4 standard, with a delay or lag of up to 3 chips. These chip values are stored in a look-up table accessible by the double-correlator 1208. The double-correlator 1208 is connected to a maximum decision unit 1210 and a frame sync unit 1212 as described above.
In summary, there is a need for an IEEE 802.15.4 compliant wireless receiver which has low power consumption and at the same time has good noise and signal-to-noise performance, for example as quantified by the noise factor nf and the minimum baseband signal-to-noise ratio in the demodulator SNRmin.